Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have nevertheless turned to copper. Most notable among the IC metalization processes that use copper is Damascene processing.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). A barrier layer that blocks diffusion of copper atoms is formed over the dielectric layer topology. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as copper that cannot readily be patterned by plasma etching.
In a typical copper IC fabrication process, the formation of the desired conductive wires on the chip begins with seed layer deposition, usually by physical vapor deposition (PVD). The seed layer provides a conformal, conductive layer on which a thicker layer of copper is electrofilled in order to fill in the features (e.g., trenches and vias) of the semiconductor wafer.
PVD has traditionally been used to form the seed layer, but does not always provide conformal step coverage, particularly with surface features having high aspect ratios (greater than about 5:1). Coverage that is not conformal is uneven; i.e., thicker in some places than others, and that may include actual gaps where the metal is discontinuous. Modern integrated circuit manufacturing has moved toward features with high-aspect ratios, particularly in advanced integrated circuits where copper is used as the conductive metal, e.g., Damascene processing. For instance, a typical via may have a diameter of 0.07 μm (the width of 266 copper atoms) but have a depth of 0.4 μm, which gives an aspect ratio of 5.7:1.
Chemical vapor deposition (CVD) is another process by which the seed layer can be deposited. However, poor nucleation of the copper at the barrier layer is a common problem with CVD, as is agglomeration. These problems result, in part, because copper itself does not adhere well to most materials. This includes titanium nitride and other materials conventionally employed as diffusion barriers. Further, the relatively high temperatures [>150° C.] required by CVD techniques of the current art aggravates the problem. Both poor nucleation and agglomeration can result in non-conformal deposition. Also, the high substrate temperature consumes a significant fraction of the thermal budget allowed for IC manufacture.
Another problem with metal deposition CVD processes arises from their carbon-containing or fluorine-containing precursor compounds, which can cause interface contamination, thus further deteriorating the adhesion of the metal layer to the underlying barrier layer. The precursor decomposition products such as carbon, organic compounds, and fluorinated compounds can become trapped in the deposited metal layer. This can lead to reliability problems where subsequent stress-inducing steps such as chemical mechanical polishing (CMP) are carried out.
Note that many of the above problems are not limited to copper seed layers. They extend to other metals and other IC fabrication process steps.